1. Field of the Invention
This invention relates to timing pulse generating circuits and, more particularly, to a timing pulse generator having particular utility in controlling the operation of a CCD imaging device.
2. Description of the Prior Art
In one type of video imaging device formed as a charge coupled device (CCD) solid-state imager, charges accumulated in strips or bands of light receiving material are transferred to a vertical shift register at the usual horizontal scanning frequency (or horizontal repetition rate). Once transferred to the vertical shift register, the charges, which represent the intensity of a video image, are transferred one line at a time at the horizontal repetition rate, to a horizontal shift register. Then, during a horizontal line interval, the charges in the horizontal shift register are shifted out at a high rate to a charge detecting element which, in turn, supplies successive voltage samples to a storage capacitor from which those successive samples are transferred to a sample-and-hold output circuit to supply successive samples of a respective line in a video image.
For proper operation of the CCD imaging device and its associated sample-and-hold output circuit, a variety of timing pulses having several different repetition rates, pulse durations and phases are used. For example, so-called horizontal transfer pulses having a frequency on the order of 4f.sub.sc, wherein f.sub.sc is the frequency of the NTSC chrominance subcarrier, 2f.sub.sc =455f.sub.H, and f.sub.H is the horizontal repetition rate, are generated to shift the charges through the horizontal shift register. Also, four separate phases of vertical shift clock pulses, each having the horizontal scanning frequency f.sub.H, are produced to shift the imaging charges through the vertical shift register to the horizontal shift register. Charge image transfer pulses having the vertical scanning frequency f.sub.V are used to transfer charges from the light receiving pick-up strips to the vertical shift register. Reset pulses of a frequency equal to 4f.sub.sc are used to reset the capacitor on which each image charge is stored temporarily; and sampling pulses also of the frequency 4f.sub.sc are used for the sample and hold operation whereby successive voltage samples corresponding to the image charges are generated by the sample-and-hold output circuit.
A timing pulse generator may be constructed as a discrete logic device, typically in the form of an integrated circuit, to generate the aforenoted diverse timing pulses. The frequency and phase relationship of these timing pulses thus are uniquely determined by the arrangement of the logic circuit from which the timing pulse generator is constructed. In the event of any differences in the frequency and/or phase relationships from one timing pulse generator to another (that is, in the event of any "scattering" of the characteristics of such generators), corrections such as phase adjustments heretofore have been attained by redesigning the entire logic circuit forming the timing pulse generator. Such redesign often is not a simple task.
To minimize circuit redesigning, it has been proposed to use a read only memory (ROM) which is addressed at relatively high speed and which stores data bits at each addressable location corresponding to the data levels of the different timing pulses at successive clock instants. For example, if each addressable location of the ROM stores a 4-bit signal, then bit 0 represents the data level at any instant of time of a first timing pulse, bit 1 represents the data level at those same instants of time of a second timing pulse, bit 2 represents the data level of a third timing pulse and bit 3 represents the data level of a fourth timing pulse. If the ROM is addressed in sequence, the 4-bit data at each addressed location is a direct indication of the change in the level of each timing pulse. Of course, the frequency at which the ROM is addressed determines the frequency of the timing pulses; and any output bit read from the ROM may be monitored so as to constitute the corresponding timing pulse.
One drawback of using a ROM to generate a variety of timing pulses is the large capacity needed to store the data bits representing the levels of those timing pulses. For example, in the NTSC system 2f.sub.sc =455f.sub.H and there are 525 lines per frame. Accordingly, an address counter used with a ROM to generate timing pulses should be able to count at least 455.times.525=238,875 bits. If N timing pulses are to be generated by the ROM, the ROM must have a capacity of N.times.238,875 bits. Hence, the address counter must be an 18-bit counter and the ROM must have a storage capacity of 2.sup.18 addressable locations. The use of a large capacity ROM and a large-scale address counter is a significant contribution to the cost and complexity of a timing pulse generator. Thus, a large capacity ROM and a large-scale counter is not desirable.